Spring Term Update

In an ongoing effort to bring everything back up to date, here’s an abridged summary of Spring 2013.

I knew it would be a crazy term far before it even began.  I am pretty sure that a first baby in the middle of ANY term would make things interesting.  But don’t think for a moment that things were only hectic after Amelia arrived.  I now know that the obstacle course that ends in parenthood (or perhaps begins with it) is a maze of constant decisions, multiple doctor appointments each week, absurd amounts of planning (for something which is largely unpredictable), more decisions, emotions, a few more decisions, a hearty amount of unfounded fears, and did I mention that there are decisions to be made every waking minute?  If it sounds like this is still a sore point it is because hands down, having to make decisions (especially between two unfavorable options, as is so often the case) is my least favorite aspect of adulthood.

Academically, I knew what I was getting myself into, which was both good and bad.  The good news was that there would be few surprises: I knew both of my professors and I knew that both classes would be useful, interesting, and fun.  The bad news was that the last term that I took courses from both Faust and Kravitz simultaneously the workload was incredibly heavy.

Amelia was born on April 18th, which I think was during week 3.  School hadn’t really reached full speed at that point, so most of what I remember from that period was a flurry of pre-delivery preparations (read: decisions) as well as an odd feeling of impending dadhood.  Because Amelia was breach, there was no choice but to perform a C-section, so in one of the strangest phone calls of our lives, Beth and I “scheduled” a baby for Thursday, April 18th.  I can’t tell the entire delivery story here, but suffice it to say the entire experience was completely unreal.  After hours of waiting pre-surgery, Amelia was out within about 5 or 10 minutes. The next 5(?) days in the hospital were also surreal, which was very likely due to the dizzying lack of restful sleep that comes with adjusting to a wake-up-every-two-hours schedule combined with the shock of a completely life-altering change.

Then I had to go back to school.  The way everything worked out, I miraculously missed almost no content in my classes, and though my professors were more than willing to offer accommodations, I don’t think I ended up needing any.

Before I knew it, finals were upon me.  My project for SystemVerilog was among the most insane projects I’ve ever done, and I am still shocked that we even pulled it off.  There were two groups of three and we decided to work together on one massive final project—we were going to synthesize a working Nintendo GameBoy, all inside an FPGA.  It was a large project, but the fact that someone had already written a working adaptation in Verilog (called FPGABoy), our task focused more around translation and verification.  My group was responsible for primarily the CPU of the system.  After weeks of struggling to even get the FPGABoy project to even open and run, we started to have doubts about the project.  The other group had run into similar issues, and by the time my group was really in the thick of it, they had dropped the idea of working with the FPGABoy codebase entirely.

We struggled and struggled, and after weeks of work we had the project somewhat running, and almost able to get the GameBoy to run in simulation—and that was after many extremely serious bugs were found and had been fixed.  We so doubted the functionality of FPGABoy after seeing the kind of errors that were present in the code that we did some research, and found (on the FPGABoy page) a message stating that the project was non-functional (which was printed in bold text).  A pretty major oversight on our part, and at that point we quickly decided to abandon the idea of getting the system working and focus only on the CPU itself, which was still a very large task.

Though FPGABoy didn’t work, the CPU used in it had been formally verified, and had actually been manufactured using the code we had access to, so we knew it had to work.  However, the project was tens of thousands of lines of code, and to make matters worse, it had been machine-translated from VHDL to Verilog—so while it was functionally identical, it was—simply put—not human readable.  Nearly every operation was on a single bit, and the code was just generally a complete clusterfuck.  Despite (or perhaps because of) the weeks of work we had poured into understanding this project, we knew that regardless of how long we continued to work on it, we could not finish it.

The turning point came less than 24 hours before the project was due, when the three of us—broken and beaten—looked at each other and decided we needed a change of plans. We had nothing to show for the 100+ hours we had dumped into getting the project working.   We started a new final project completely from scratch and didn’t look back.  We worked furiously through most of the night, hopped up on soda and panic, stopping only to eat shitty McDonalds food so we had sustenance to function.  It’s all still a blur.  The next day, we somehow had a project on our hands that rivaled the quality of most others in the class, yet was completed in literally one huge hack session that started less than a day prior.

I still don’t know how it all happened, but somehow I survived.  I built a (sort of) functional Skittles-sorting machine for my other class, but I actually still have plans to work on it, so I will have to wait until later to post anything about that.